1. Field of the Invention
The present invention relates to a semiconductor memory device that has a memory cell array having a plurality of memory cells arranged in a row direction and a column direction respectively, each memory cell including a variable resistance element that stores information based on an electrical operating characteristic that an electric resistance changes by applying electrical stress. More specifically, the present invention relates to a technique of preventing and suppressing degradation of an electrical operating characteristic of a variable resistance element attributable to programming and erasing operations.
2. Description of the Related Art
A nonvolatile semiconductor memory device as represented by a flash memory is being used as a large-capacity and compact information recording medium in a wide range of fields such as computers, communications, measuring devices, automatic control devices, and daily equipment that is used in the individuals' environments. Demand for a lower-cost and larger-capacity nonvolatile semiconductor memory device is very high. A main reason is assumed that the nonvolatile semiconductor memory device can exhibit functions as a memory card, a mobile phone, and the like that can be easily carried, or as a data storage, a program storage, and the like that store data in a nonvolatile manner as initial setting of a device operation, because the nonvolatile semiconductor memory device can electrically write data and also because the device can keep a nonvolatile characteristic that data is not erased even after a power supply is disconnected.
A mobile phone is pointed out as a representative application device of a flash memory. In a condition that a large capacity-constraint is applied to a power supply because of an extremely strong demand for miniaturization of a mobile phone, for example, a nonvolatile flash memory that does not require a backup power supply to hold information even during a long waiting time is suitable. Further, based on an enlarged memory capacity of a flash memory itself, the flash memory can store many application programs and many pieces of data, and can perform application programs by changing over between them, thereby contributing to multifunctioning of a mobile phone.
In the semiconductor memory device described above, because of a tendency of an increasing size of an application program and data themselves, a practical application of a system that can write software stored in the semiconductor memory device, can correct bugs, and can upgrade functions is required in the future. However, a conventional flash memory requires a very long time to write data, and therefore, there is a limit to an amount of data that can be written at one time. Further, there is a problem in that a data write procedure becomes very complex, such as for example, it is necessary to secure an additional storage area to buffer a file.
Further, it is predicted that, in principle, a flash memory has a limit in miniaturization, and a new-type nonvolatile semiconductor memory device that replaces the flash memory is being widely studied. Among others, a resistance random-access semiconductor memory, which uses a phenomenon that an electric resistance changes when a voltage is applied to a metal oxide film, is very advantageous as compared with a flash memory in the point of the miniaturization limit, and also high-speed data writing is possible. Therefore, researches and developments are actively progressed.
Taking an example, a method of reversibly changing an electric resistance by applying a voltage pulse to a Perovskite material which is known as a colossal magnet resistance effect by S. Liu and A. Ignatiev, et al. of the University of Houston, U.S. is disclosed in U.S. Pat. No. 6,204,139, and “Electric-pulse-induced reversible resistance change effect in magnetoresistive films”, by Liu, S. Q., et al., Applied Physics Letter, Vol. 76, pp. 2749-2751, 2000. This is a remarkable breakthrough achievement in that a resistance change over several digits appears even at a room temperature without application of a magnetic field while using a Perovskite material known as the colossal magnet resistance effect. A RRAM (Resistance Random Access Memory) as a resistance nonvolatile memory that uses a variable resistance element utilizing this phenomenon does not use a magnetic field at all unlike an MRAM, and therefore, has excellent characteristics in that power consumption is extremely low, miniaturization and high integration are easy, and that multilevel storage is possible because of a remarkably wide dynamic range of a resistance change as compared with that of the MRAM. A basic structure of an actual device is extremely simple, and FIG. 31 shows a configuration of this device.
As shown in FIG. 31, a variable resistance element has such a structure that a lower electrode 103, a variable resistor 102, and an upper electrode 101 are sequentially stacked in this order. The variable resistance element has a characteristic that it can reversibly change a resistance value when a voltage pulse is applied between the upper electrode 101 and the lower electrode 103. By reading a resistance value that changes based on this reversible resistance change operation (hereinafter referred to as “switching operation”), a novel semiconductor memory device can be achieved.
As other variable resistance element, an element that uses an oxide of a transition metal element such as a titanium oxide (TiO2) film, a nickel oxide film (NiO) film, a zinc oxide (ZnO) film, and a niobium oxide (Nb2O5) film also exhibits a reversible resistance change, as is known from Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2002-537627, and “Bistable Switching in Electroformed Metal-Insulator-Metal Devices”, by H. Pagnia, et al., Phys. Stat. Sol. (a), vol. 108, pp. 11-65, 1988. A phenomenon of a switching operation that uses NiO is reported in detail in “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses”, by Baek, I. G., et al., IEDM2004, pp. 587-590, 2004.
A semiconductor memory device can be configured by forming a memory cell array by having a plurality of memory cells arranged in a row direction and a column direction respectively in a matrix shape, each memory cell including a variable resistance element configured by the variable resistor described above and storing information by changing an electric resistance of the variable resistance element, and by arranging, around the memory cell array, a circuit that controls programming, erasing, and reading of data to/from each memory cell of the memory cell array.
This semiconductor memory device is configured by forming a memory cell array by having a plurality of memory cells arranged in a row direction and a column direction respectively in a matrix shape, each memory cell including a variable resistance element, and also by having arranged a peripheral circuit that controls programming, erasing, and reading operations of data to and from each memory cell of the memory cell array. For this memory cell, there are a memory cell (called “1T/1R type”) that is configured by one select transistor T and one variable resistance element R, and a memory cell (called “1R type”) that is configured by only one variable resistance element R, depending on a difference of a constituent element of each memory cell. Among these, FIG. 32 shows a configuration example of the 1T/1R type memory cell. For the 1T/1R type memory cell, two types of configuration can be considered depending on which one of a variable resistance element and a select transistor is connected to a bit line side (for example, see Japanese Unexamined Patent Publication No. 2004-185755 and Japanese Unexamined Patent Publication No. 2004-185754).
FIG. 32 schematically shows a configuration example of a memory cell array 15b of the 1T/1R type memory cells. In this memory cell array configuration, the memory cell array 15b has m×n memory cells 2 arranged at cross points of m bit lines (BL1 to BLm) that extend in a column direction, and n word lines (WL1 to WLn) that extend in a row direction. In addition, n source lines (SL1 to SLn) are arranged in parallel with the word lines. In each memory cell, an upper electrode of a variable resistance element 12 and a drain of a select transistor 13 are connected together, a lower electrode of the variable resistance element 12 is connected to a bit line, a gate electrode of the select transistor 13 is connected to a word line, and a source of the select transistor 13 is connected to a source line.
By configuring a memory cell 14b in a series circuit of the select transistor 13 and the variable resistance element 12 in this manner, the select transistor 13 of the memory cell 14b that is selected based on a potential of a word line becomes an ON state, and further, a program voltage or an erase voltage is selectively applied to only the variable resistance element 12 of the memory cell 14b that is selected based on a potential of a bit line, thereby making it possible to change a resistance value of the variable resistance element 12.
In a memory cell array that is configured by the 1T/1R type memory cells, when selecting a memory cell from which or to which data is to be read, programmed, and erased, a predetermined bias voltage is applied to a selected word line and a selected bit line respectively, and only a select transistor that is included in a selected memory cell connected to both the selected word line and the selected bit line is set to an ON state. With this arrangement, a read current and program/erase currents can be passed to only a variable resistance element that is included in the selected memory cell. Therefore, by including the select transistor in the memory cell, a configuration of a peripheral circuit which is similar to a conventional flash memory can be used.
Next, a configuration example of a large-capacity semiconductor memory device that has a memory cell array formed by the 1R type memory cells will be described with reference to the drawings.
As shown in FIG. 33, each memory cell 14a is not configured by a series circuit of a select transistor and a variable resistance element, but is configured by a single unit of the variable resistance element 12. A memory cell array 15a is configured by arranging the 1R type memory cells 14a in a matrix shape. This is similar to a memory cell array that is disclosed in Japanese Unexamined Patent Publication No. 2004-185755, for example. Specifically, the memory cell array 15a is configured to have m×n memory cells 14a arranged at cross points of m bit lines (BL1 to BLm) that extend in a column direction and n word lines (WL1 to WLn) that extend in a row direction. In each memory cell 14a, an upper electrode of a variable resistance element 3 is connected to a word line, and a lower electrode of the variable resistance element 3 is connected to a bit line.
According to the memory cell array 15a configured by the 1R type memory cells 14a, in selecting a memory cell from which data is to be read, a similar bias voltage is also applied to a selected memory cell that is connected to a word line and a bit line common to the memory cell from which data is to be read. Therefore, a read current also flows through a memory cell other than the memory cell from which data is to be read. The read current that flows through the selected memory cell which is selected in units of rows or columns is detected as the read current of the memory cell from which data is to be read, by a column selection or a row selection. In a memory cell array 15 that is configured by 1R type memory cells 14, a read current also flows through a memory cell other than a memory cell from which data is to be read. However, this has an advantage in that a memory structure is simple and that a memory cell area and a memory cell array area become small.
FIG. 34 shows a conventional example of a voltage application procedure to each unit in a data reading operation of the memory cell array 15 that is configured by the 1R type memory cells 14. In reading data from a selected memory cell, a selected word line which is connected to the selected memory cell is maintained at a ground potential Vss, and a read voltage Vr is applied to all other unselected word lines and all bit lines during a reading period Tread. Because a voltage difference of the read voltage Vr is generated between the selected word line and all the bit lines during the reading period Tread, a read current corresponding to an electric resistance, that is, a memory state, flows through a variable resistance element of the selected memory cell, and data stored in the selected memory cell can be read. In this case, because the read current corresponding to a memory state of the selected memory cell which is connected to the selected word line flows through each bit line, data of a specific selected memory cell can be read by selectively reading the read current that flows through a predetermined selected bit line, at a bit line side. In this case, arrangement can be such that the read current that flows through each word line is selectively read at the word line side, by replacing a relationship between the bit lines and the word lines.
FIG. 35 shows a configuration example of a semiconductor memory device that includes a memory cell array 15a of the 1R type memory cells 14a. A specific memory cell within the memory cell array 15a corresponding to an address input that is inputted from an address line 18 to a control circuit 20 is selected by a bit line decoder 16 and a word line decoder 17, each operation of data programming, erasing, and reading is performed, and data is stored and read to and from a selected memory cell. Input/output of data between an external device (not shown) and the semiconductor memory device is performed via a data line 19.
The word line decoder 17 selects a word line of the memory cell array 15a corresponding to a signal inputted to the address line 18, and the bit line decoder 16 selects a bit line of the memory cell array 15a corresponding to an address signal inputted to the address line 18. The control circuit 20 controls each operation of programming, erasing, and reading of the memory cell array 15a. The control circuit 20 controls the word line decoder 17, the bit line decoder 16, a voltage application circuit 22 based on an address signal inputted from the address line 18, a data input signal (during programming) inputted from the data line 19, and a control input signal inputted from the control signal line 21 to perform each operation of reading, programming, and erasing of the memory cell array 15a. In the example shown in FIG. 35, although not shown in the figure, the control circuit 20 includes functions as a general address buffer circuit, a data input/output buffer circuit, and a control input buffer circuit.
The voltage application circuit 22 switches, corresponding to an operation mode, each voltage of a word line, a bit line, and a source line that are necessary to read, program, and erase in the memory cell array 15a, and supplies the switched voltage to the memory cell array 15a. In this case, Vcc denotes a power supply voltage of the semiconductor memory device, Vss denotes a ground voltage, Vwrt and Vrst denote a program voltage and an erase voltage, and Vr denotes a read voltage. Data is read from the memory cell array 15a via the bit line decoder 16 and a reading circuit 23. The reading circuit 23 determines a data state, transfers the determination result to the control circuit 20, and outputs the result to the data line 19.
Here, the variable resistance element is based on a phenomenon that the variable resistance element becomes a low resistance state or a high resistance state, when an area (hereinafter appropriately referred to as “filament path”) is formed in which resistivity locally decreases in the variable resistor due to a heat increase by a current flowing through the variable resistance element, or when the filament path is broken, depending on a voltage application condition.
To achieve the switching operation, first, it is necessary to form a filament path by applying a voltage which is required to be higher than a voltage in a normal switching operation to a variable resistance element immediately after manufacturing the variable resistance element (hereinafter referred to as “forming process”). In this forming process, in the case of configuring a variable resistor by a metal oxide, for example, a high voltage which is a few times to ten times higher than a normal operation voltage is applied to a metal oxide that is basically substantially an insulator, for a certain period of time or more. In this manner, a current path is considered to be almost forcibly formed in the insulator. This occurs because an element before forming is basically an insulator, or because at least a part of the current path near an electrode interface is originally an insulator.
Since this forming process is a process of forcibly forming a current path in an insulator, a switching characteristic of a variable resistance element that is achieved through this process tends to be unstable, and resistance value control becomes difficult.
That is, since the resistance value of the variable resistance element depends on a formation of the filament path, the resistance value of the variable resistance element varies due to a change in diameter of the filament path and a filament density because of increase in the number of times of switching operation. There is a problem that an element in a low resistance state does not have area dependence. When the number of times of switching operation increases, a variation of a resistance value becomes large, and resistance value control of the variable resistance element becomes difficult.